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# my first Makefile in Tcl
target foo.o foo.cc {
$CC $CCFLAGS -o $TARGET $SRC
}
If you know make and/or Tcl, the above example should look
familiar. It defines that the file foo.o can be created from
foo.C by calling a C++ compiler (stored in the variable $CC)
with some flags.
A typical TMakefile in a large project looks like this:
# using modules in a project
module {cxx qt math}
lappend PROGRAMS testA testB
lappend PROJLIBS otherProj1/xy/abc otherProj2/aa/bb
This example would search for all C++ source files, compile them,
search for all header files using QT and precompile them using
moc, put all but testA.o and testB.o into a
library, create the executables testA and testB, and
link them with the local lib as well as with the specified libraries
from other project directories. These other project are located either
in the same project root directory as the current project, or they may
reside in completely different locations specified in a project
location path variable.
And what's even more important: this works exactly this way on many platforms (e.g. Linux, IRIX, SunOS, Windows), and you can even compile on many platforms at the same time. tmk will put all generated files into an architecture-dependent target directory. All platform- and site specific detail is hidden from the actual TMakefile, and handled by a central configuration subsystem.
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